Forksheet FET - the future of transistor manufacturing?


Metrology development to meet fast evolving devices


With continuously shrinking transistor sizes and new structures, new metrological challenges also arise, including the detection of different structural defects. In the world of complementary metal-oxide semiconductor (CMOS) technology, there are ever-increasing demands for more efficient and faster devices, which include the development of even smaller and more complex transistors.

For a while now nano-sheet FETs were considered the top of modern device making, but the key to successfully shrink the size of the transistors is projected to be the appearance of forksheet field-effect transistor (FET) based devices. Forksheet FET is an advanced variation of the nanosheet architecture, where a dielectric wall is added between the n-channel metal-oxide semiconductor (NMOS) and p-channel metal-oxide semiconductor (PMOS) devices, allowing a tighter arrangement. Based on simulations this is projected to enable a performance increase of up to 10%, a 24% energy efficiency improvement and reduced cell area by 20% compared to a nanosheet FET.1 However, it is crucial to emphasize that despite these improvements, the dimensions of defects occurring within the structure remain unchanged, thereby amplifying their impact. Consequently, efficient and accurate metrology solutions are increasingly essential to timely detect these defects, ensuring optimal device manufacturing processes.

The European semiconductor community is keen to increase its market presence and strengthen its position as a technology innovator in the global semiconductor industry, with a strong focus on projects that foster technological advancements, provide vital information exchange, and enhance knowledge sharing to refine device manufacturing processes. Within the frame of the IT2 EU project, Semilab published paper on ’Detection of structural asymmetries in Forksheet FET arrays using Mueller matrix ellipsometry: a theoretical study’ based on the recent development results by the spectroscopic ellipsometry experts of Semilab. Their work required to develop generalized ellipsometry methods and system to measure data that is complementary to conventional OCD, such as line roughness, pitch-walking, bending or other irregularities.

To the above mentioned forksheet FET samples’ characterization, the team carried out standard spectroscopic ellipsometry measurements. After the evaluation they reached to Mueller matrix (MM) measurement, as it can provide an opportunity to investigate and provide even better results on asymmetries in the material.

The team’s approach was to create a simulation of MM measurements with different degrees and directions of forksheet FET’s profile asymmetries, to quantify the distinguishability of the optical responses caused by the defects and calculate the correlation between the asymmetry parameters was. Since the precise alignment of a sample is a key factor in the detection of asymmetries, the effect of the alignment uncertainty and a method for filtering it out were also investigated.
Keep reading the full study HERE.